As the channel length of MOSFETs (Metal Oxide Field-effect Transistors) has been scaled increasingly, a series of effects, which are ignorable in an MOSFET long-channel model, are becoming more and more significant and are even becoming a dominant factor in affecting performance, and are collectively referred to as the short-channel effects. The short-channel effects tend to deteriorate the electrical performance of a device, for example causing the problems of reducing the threshold voltage of a gate, increasing the power consumption, and reducing the signal to noise ratio, etc.
In order to control the short-channel effects, more dopant elements (such as phosphorus, boron, etc.) have to be doped into the channel. However, this tends to lead to reduced carrier mobility in the channel of a device. There also exists problems to control the steepness of the profile for the dopants to be doped into the channel, which tends to cause severe short-channel effects. Secondly, the traditional SiGe PMOS strained silicon technology also encounters a bottleneck, making it difficult to provide stronger strain for the channel. Furthermore, there is also a bottleneck for the thickness of a gate oxide dielectric, and it is difficult for the speed in reducing the thickness of the gate oxide to keep pace with that in reducing the gate width, resulting in a larger leaking current of the gate dielectric. The critical dimensions are reduced continuously, possibly causing continued increase of the resistance for the source/drain regions and higher power consumption of the device.
Currently, the dominant thinking in the industry is to improve the traditional planar device technology, reduce the thickness of the channel region, and eliminate the intermediate layer on the bottom of a depletion layer in the channel, so that the depletion layer in the channel may fill up the whole channel region, which is the so-called fully depleted (FD) device, while the traditional planar devices belong to the partially depleted (PD) devices.
However, in order to fabricate a fully depleted device, it requires extremely thin thickness of silicon layer at the channel. The traditional manufacturing process, particularly the traditional bulk silicon-based manufacturing process, has difficulties in producing a structure meeting such requirements or has high costs. Even in terms of the emerging SOI (Silicon-On-Insulator) process, the thickness of the channel silicon layer is still difficult to be controlled at a relatively thin level. Regarding the complete concept of the realization for a fully depleted device, the focus of R&D efforts is turning to the stereoscopic device structure, i.e., to the fully depleted dual-gate or tri-gate technology.
The stereoscopic device structure (also referred to as a vertical device in some documents) refers to the technology in which the cross sections of the source/drain regions and of the gates of a device are not located within the same plane, and it belongs to a FinFet (Fin Field-effect Transistor) structure.
After turning to the stereoscopic device structure, the channel region is no longer compriseed in the bulk silicon or SOI, and becomes independent from these structures. Therefore, the fully depleted channel with extremely thin thickness may be fabricated by means of etching, etc.
FIG. 1 shows a currently proposed stereoscopic semiconductor device, the semiconductor device comprising: a semiconductor substrate 20, the semiconductor substrate 20 is located on an insulating layer 10; source/drain regions 30, the source/drain regions 30 abut a first set of opposite side surfaces 22 of the semiconductor substrate 20; gates 40 located on second side surfaces 24 of the semiconductor substrate 20 abutting the first side surfaces 22 (a gate dielectric layer and a work function metal layer sandwiched between the gates 40 and the semiconductor substrate 20 are not shown in the figure). In this case, in order to reduce the resistance of the source/drain regions, the edge of the source/drain regions 30 may be extended, i.e., the width of the source/drain regions 30 (in the xx′ direction) is larger than the thickness of the semiconductor substrate 20. Therefore, with the increase of the width (d) of the source/drain regions 30, the parasitic capacitances between the source/drain regions 30, the gates 40 and the semiconductor substrate 20 increase, thus increasing the delay by the resistance and the capacitance or decreasing the alternative current performance of the device.